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US 2024/0176407 A1Published application
Storage device for executing background operation based on power state and operating method thereof
AssigneeSK hynix Inc.
InventorIn Jong JANG
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Abstract
A storage device may enter a plurality of intermediate power states sequentially while entering from a first power state to a second power state. The storage device may check background flag information while entering each of the plurality of intermediate power states, and execute a target background operation, executable in a first intermediate power state, based on the background flag information.
Claims17
A storage device comprising:
- a memory including a plurality of memory blocks;
- and
- a controller configured to:
- enter a plurality of intermediate power states sequentially while transitioning from a first power state to a second power state,
- check background flag information indicating background operations executable in each of the plurality of intermediate power states when entering each of the plurality of intermediate power states, and
- execute a target background operation, executable in a first intermediate power state, among the executable background operations based on the background flag information, after entering the first intermediate power state and before entering a second intermediate power state.
3 more elements
A method for operating a storage device, comprising:
- entering a first intermediate power state among a plurality of intermediate power states that are entered sequentially while transitioning from a first power state to a second power state;
- checking background flag information indicating background operations executable among a plurality of background operations;
- executing a target background operation executable in the first intermediate power state based on the background flag information;
- and
- determining whether to enter a second intermediate power state.
2 more elements
A controller comprising:
- a memory interface capable of communicating with a memory including a plurality of memory blocks;
- and
- a control circuit configured to:
- enter a plurality of intermediate power states sequentially while transitioning from a normal state consuming a first power to a low power state consuming a second power, which is less than the first power, and
- execute, while entering each of the plurality of intermediate power states, an executable background operation from among a plurality of background operations based on background flag information indicating executable background operations.
2 more elements
Dependencies are inferred from the claim text.