Methods and systems of operating a pnp bi-directional double-base bipolar junction transistor

A switch assembly comprising:

• an upper terminal, a lower terminal, and an upper-control input;
• a transistor defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter;
• an upper-main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper base, and a gate;
• a lower-main FET defining a first lead coupled to the lower base, a second lead coupled to the lower terminal, and a gate;
• a controller coupled to the upper-control input, the gate of the upper-main FET, and the gate of the lower-main FET, and for a first applied voltage across the upper terminal and lower terminal, the controller configured to:
• assert the gate of the upper-main FET to make the upper-main FET conductive, arrange the transistor for conduction from the upper base to the lower base, and assert the gate of the lower-main FET to make the lower-main FET conductive such that a first load current flows from the upper terminal to the lower terminal;
• sense de-assertion of the upper-control input;
• and responsive to de-assertion of the upper-control input
• de-assert the gate of the lower-main FET to interrupt the first load current from the lower base.