Semiconductor device with backside interconnection and method for forming the same

A method of forming a memory circuit, comprising:

• forming a first active region and a second active region over a substrate;
• forming a gate structure over the substrate, wherein the gate structure has a first portion engaging the first active region in forming a first pull-down transistor of the memory circuit and a second portion engaging the second active region in forming a second pull-down transistor of the memory circuit;
• forming a gate-cut feature isolating the first and second portions of the gate structure;
• forming a first source/drain feature of the first pull-down transistor and a second source/drain feature of the second pull-down transistor, wherein the first and second source/drain features are disposed on two opposing sides of the gate-cut feature;
• selectively etching the first and second active regions from a backside of the substrate to form a trench, wherein the trench exposes bottom surfaces of the first and second source/drain features and the gate-cut feature;
• and
• depositing a conducive material in the trench to form a backside conductive feature landing on the bottom surfaces of the first and second source/drain features and the gate-cut feature.

A semiconductor structure, comprising:

• first and second active regions extending lengthwise along a first direction;
• a gate stack extending lengthwise along a second direction perpendicular to the first direction;
• a dielectric feature extending lengthwise along the first direction and disposed between the first and second active regions, wherein the dielectric feature divides the gate stack into a first segment over the first active region and a second segment over the second active region;
• a first epitaxial feature disposed on the first active region;
• a second epitaxial feature disposed on the second active region, wherein the first and second epitaxial features are disposed on two opposing sides of the dielectric feature;
• and
• a backside conductive feature electrically coupled to the first and second epitaxial features, wherein the backside conductive feature includes a first leg portion landing on a bottom surface of the first epitaxial feature, a second leg portion landing on a bottom surface of the second epitaxial feature, and a middle portion physically connecting the first and second leg portions, wherein the middle portion is directly under the dielectric feature.