Method of fabricating an electronic chip including a memory circuit
AssigneeSTMicroelectronics (Crolles 2) SAS
InventorsOlivier WEBER, Remy BERTHELON
Life of this patent
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Abstract
A method of manufacturing an electronic chip includes the following successive steps: a) forming of a first layer on top of and in contact with a second semiconductor layer, the second layer being on top of and in contact with a third semiconductor layer; b) doping of the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type; c) forming of islands in the first layer organized in an array of rows and of columns at the surface of the second layer; and d) forming of memory cells based on a phase-change material on the islands of the first layer.
Claims20
A method, comprising:
- forming a first layer on top of and in contact with a second doped semiconductor layer of a first conductivity type, the second layer being on top of and in contact with a third doped semiconductor layer of a second conductivity type opposite to the first conductivity type;
- doping the first layer to form, on the second layer, a first doped sub-layer of the first conductivity type and a second doped sub-layer of the second conductivity type;
- forming islands in the first layer organized in an array of rows and columns at the surface of the second layer;
- and
- forming memory cells based on a phase-change material on the islands of the first layer, the second layer, the third layer, and the second sub-layer of the first layer forming a bipolar transistor.
An electronic chip, comprising:
- a first doped semiconductor layer of a first conductivity type;
- a second doped semiconductor layer of a second conductivity type opposite the first conductivity type on top of and in contact with the first doped semiconductor layer;
- islands organized in an array of rows and of columns on the surface of the second doped semiconductor layer, each island including a first doped sub-layer of the second conductivity type on the second doped semiconductor layer and a second doped sub-layer of the first conductivity type on the first doped sub-layer;
- a plurality of memory cells based on a phase-change material each on top of a respective island;
- and
- a bipolar transistor formed of the first doped semiconductor layer, the second doped semiconductor layer, and the second doped sub-layer of the islands.
A method, comprising:
- forming a first doped layer of semiconductor material of a first conductivity type;
- forming a second doped layer of semiconductor material of a second conductivity type opposite to the first conductivity type on top of and in contact with the first doped layer;
- forming a third doped layer on top of and in contact with the second doped layer, the third doped layer including a first doped sub-layer of the second conductivity type on the second doped layer and a second doped sub-layer of the first conductivity type on the first doped sub-layer;
- patterning the third doped layer to form a plurality of islands arranged in rows and columns on the second doped layer;
- surrounding each island with a respective electrically insulating spacer;
- forming a layer of semiconductor material between the islands after forming the electrically insulating spacers;
- and
- forming a plurality of phase-change memory cells each on top of a respective island, a bipolar transistor being formed of the first doped layer, the second doped layer, and the second doped sub-layer of the islands.
Dependencies are inferred from the claim text.