Efficient floating point squarer

Hardware logic arranged to square a floating point number, the floating point number comprising an m-bit input exponent and an input mantissa, the hardware logic comprising:

• mantissa hardware logic arranged to generate a candidate mantissa output by squaring the input mantissa;
• exponent and exception logic arranged to generate three candidate exponent outputs, the three candidate exponent outputs comprising an exceptional exponent output, an exponent output generated from the m-bit input exponent and an incremental exponent, wherein the incremental exponent is generated by incrementing the exponent output generated from the m-bit exponent;
• a first multiplexer arranged to select, as an output mantissa, either the candidate mantissa output or an exceptional mantissa output based on exception signals generated by the exponent and exception logic based on the m-bit input exponent;
• and
• a second multiplexer arranged to select, as an output exponent, one of the three candidate exponent outputs based on the exception signals generated by the exponent and exception logic and based on a signal indicating a mantissa overflow condition.