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US 2024/0128982 A1Published application
Hardware acceleration of data reduction operations
AssigneeIntel Corporation
InventorsSmita Kumar, Patrick Fleming
Life of this patent
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Abstract
A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.
Claims20
An apparatus comprising:
- a hardware accelerator device comprising:
- one or more interfaces to receive a request to perform one or more data reduction operations on a data;
- transform circuitry to apply a set of reversible data transforms on the data based on the request to generate transformed data;
- and
- compression circuitry to compress the transformed data to generate compressed transformed data;
- and
- output circuitry to generate an output of the one or more data reduction operations, the output comprises the compressed transformed data and transform metadata, and the transform metadata indicates the set of reversible data transforms applied to the compressed transformed data.
4 more elements
A method comprising:
- receiving, at a hardware accelerator in a system, a request to perform one or more data reduction operations on data;
- applying one or more reversible data transforms on the data, using hardware circuitry of the hardware accelerator, based on the request to generate transformed data;
- compress the transformed data, using hardware circuitry of the hardware accelerator, to generate compressed transformed data;
- and
- generating an output of the one or more data reduction operations, wherein the output comprises the compressed transformed data and transform metadata, and the transform metadata indicates the one or more reversible data transforms applied to the compressed transformed data.
2 more elements
A system comprising:
- a processor device;
- a memory;
- a hardware accelerator coupled to the processor device and the memory, wherein the hardware accelerator comprises circuitry to:
- receive a request to perform data reduction on particular data in the memory, wherein the request identifies as set of reversible data transforms to be applied to the particular data prior to compression of the particular data;
- apply the set of reversible data transforms to the data to generate transformed data;
- compress the transformed data to generate compressed transformed data;
- and
- generate an output to comprise the compressed transformed data and transform metadata, wherein the transform metadata indicates the set of reversible data transforms applied to the compressed transformed data.
5 more elements
Dependencies are inferred from the claim text.