Slew Rate Control Circuit Capable of Providing Stable Performance and Stable Duty Cycle

A slew rate control circuit comprising:

• a slew rate control unit comprising:
• a first input terminal configured to receive a first control signal;
• a second input terminal configured to receive a second control signal;
• a third input terminal configured to receive a third control signal;
• and
• an output terminal configured to output a plurality of control voltages;
• a capacitive delay unit coupled to the slew rate control unit and configured to receive an input signal;
• a delay unit coupled to the capacitive delay unit;
• a first output unit comprising:
• an input terminal coupled to the capacitive delay unit and configured to receive the input signal;
• a first output terminal configured to output a first output signal;
• and
• a second output terminal configured to output a second output signal;
• a second output unit comprising:
• a first input terminal coupled to the capacitive delay unit and configured to receive an output of the capacitive delay unit;
• a second input terminal configured to receive the second control signal;
• and
• an output terminal configured to output a third output signal;
• and
• a third output unit comprising:
• a first input terminal coupled to the delay unit and configured to receive an output of the delay unit;
• a second input terminal configured to receive the third control signal;
• and
• an output terminal configured to output a fourth output signal.