Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus

An automatic test pattern generation apparatus, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, and the at least one processor is configured to read a computer program stored in the at least one memory, to perform the following steps:

• determining a to-be-detected first logic cone from a fan-out logic cone corresponding to a target line, wherein the fan-out logic cone is a region formed by a gate circuit that passes from the target line to an output end of the circuit under test;
• determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line, wherein the fan-in logic cone is a region formed by a gate circuit that passes from an input end of the circuit under test to the target line, and the second logic cone is a region that is in the fan-in logic cone and that is formed by a gate circuit that affects an output value of the first logic cone;
• generating a first conjunctive normal form (CNF) based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result, wherein the first detection result indicates a fault type of the target line;
• and
• if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.