Decoding fec codewords using ldpc codes defined by a parity check matrix which is defined by rpc and qc constraints

A decoder comprising:

• a processor configured to receive encoded input data including forward error correction (FEC) codewords, and to perform a plurality of decoding iterations to decode the FEC codewords using a parity check matrix, the processor comprising
• a plurality of check node processing circuits, each of which configured, during each of the plurality of decoding iterations, to concurrently i) receive and begin processing a new set of values that are at least partially indicative of one of the FEC codewords, and ii) based on the parity check matrix, complete processing of a previously received set of values at least partially indicative of the one of the FEC codewords to generate a first message, the previously received set of values received prior to the new set of values, and
• a plurality of variable node processing circuits configured, during each of the plurality of decoding iterations, to generate second messages based on the first messages and the parity check matrix;
• and
• an output circuit configured to output a decoded codeword based on the second messages.