Video processing circuit and associated video processing method
AssigneeSigmastar Technology Ltd.
InventorXiao-Ding ZHU
Life of this patent
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Abstract
The present invention discloses a video processing circuit, which is coupled to a memory chip and includes an image processing circuit. The image processing circuit includes a first channel, a second channel and a compression circuit. The two channels process first image data and second image data to generate first processed image data and second processed image data, respectively. The compression circuit compresses the first processed image data and the second processed image data to generate first compressed image data and second compressed image data, respectively. A memory block in the memory chip is configured as a ring buffer shared by the first channel and the second channel so as to store the first compressed image data and the second compressed image data.
Claims13
A video processing circuit, coupled to a memory chip, comprising:
- an image processing circuit, comprising:
- a first channel and a second channel, the first channel and the second channel sharing an input port, wherein the first channel processes first image data to generate first processed image data, and the second channel processes second image data to generate second processed image data;
- and
- a compression circuit, configured to compress the first processed image data and the second processed image data to generate first compressed image data and second compressed image data, respectively;
- wherein a memory block in the memory chip is configured as a ring buffer, which is shared by the first channel and the second channel to store the first compressed image data and the second compressed image data.
A video processing method, applied to a video processing circuit coupled to a memory chip, the video processing method comprising:
- processing first image data by a first channel of an image processing circuit of the video processing circuit to generate first processed image data, and processing second image data by a second channel of the image processing circuit to generate second processed image data, wherein the first channel and the second channel share an input port;
- compressing the first processed image data and the second processed image data to generate first compressed image data and second compressed image data, respectively;
- and
- storing the first compressed image data and the second compressed image data to a ring buffer;
- wherein a memory block in the memory chip is configured as a ring buffer, which is shared by the first channel and the second channel to store the first compressed image data and the second compressed image data.
Dependencies are inferred from the claim text.