Semiconductor device

A semiconductor device configured by bonding a first chip and a second chip together, the semiconductor device comprising:

• a first signal output circuit provided at both the first chip and the second chip and driven by a first drive power;
• a second signal output circuit provided at both the first chip and the second chip and driven by a second drive power different from the first drive power;
• a first phase comparison circuit, provided at the first chip, which compares a phase of a first signal with a phase of a second signal, wherein:
• the first signal is output from the first signal output circuit provided at the first chip and input directly to the first phase comparison circuit, and
• the second signal is output from the first signal output circuit provided at the first chip and input to first phase comparison circuit the via the first signal output circuit provided at the second chip;
• a second phase comparison circuit that is provided at the second chip, and that compares a phase of a third signal with a phase of a fourth signal, wherein:
• the third signal is output from the first signal output circuit provided at the first chip, transmitted to the second chip, and input directly to the second phase comparison circuit, and
• the fourth signal is output from the first signal output circuit provided at the first chip, transmitted to the second chip, and input to the second phase comparison circuit via the first signal output circuit provided at the second chip;
• a third phase comparison circuit, provided at the first chip, that compares a phase of a fifth signal with a phase of a sixth signal, wherein:
• the fifth signal is output from the second signal output circuit provided at the first chip and input directly to the third phase comparison circuit, and
• the sixth signal is output from the second signal output circuit provided at the first chip and input to the third phase comparison circuit via the second signal output circuit provided at the second chip;
• and
• a fourth phase comparison circuit, provided at the second chip, that compares a phase of a seventh signal with a phase of an eighth signal, wherein:
• the seventh signal is output from the second signal output circuit provided at the first chip and transmitted to the second chip, and input directly to the fourth phase comparison circuit, and
• the eighth signal is output from the second signal output circuit provided at the first chip and transmitted to the second chip, and input to the fourth phase comparison circuit via the second signal output circuit provided at the second chip after being.