Bignum addition and/or subtraction with carry propagation

A method comprising:

• adding, by a plurality of adders, first and second X bit binary portion values of first and second Y bit binary values to generate first carry bits, with Y being a multiple of X;
• generating, by a plurality of carry bit generation circuits, second carry bits based on the first carry bits;
• and
• utilizing the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.

A processing unit comprising:

• a first vector register to store a first Y bit binary value comprising a plurality of first X bit binary portions, with Y being a multiple of X;
• a second vector register to store a second Y bit binary value comprising a plurality of second X bit binary portions;
• a plurality of adders to add first and second X bit binary portion values of the first Y bit binary value and the second Y bit binary value to generate first carry bits;
• and
• a plurality of carry bit generation circuits, coupled to the plurality of adders, respectively, to receive the first carry bits and generate second carry bits based on the first carry bits;
• wherein the plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.