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US 2024/0107741 A1Published application
Memory Device Comprising an Electrically Floating Body Transistor
AssigneeZeno Semiconductor, Inc.
InventorsYuniarto Widjaja, Jin-Woo Han
Life of this patent
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Abstract
A semiconductor memory cell having an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
Claims17
1-24. (canceled)
A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region on opposite sides of said floating body region;
- a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region;
- and
- an access transistor, wherein said access transistor comprises said well region;
- a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;
- wherein said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and a depletion region formed as a result of an application of a back bias to said buried layer region;
- and
- wherein said well region of said access transistor is electrically connected to said buried layer region.
10 more elements
A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region on opposite sides of said floating body region;
- a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region;
- and
- an access transistor, wherein said access transistor comprises said well region;
- a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;
- wherein said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and a depletion region formed as a result of an application of a back bias to said well region;
- and
- wherein said well region of said access transistor is electrically connected to said buried layer region.
10 more elements
An integrated circuit comprising:
- a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region on opposite sides of said floating body region;
- a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region;
- an access transistor, wherein said access transistor comprises said well region;
- and
- a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;
- wherein said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and a depletion region formed as a result of an application of a back bias to said semiconductor memory cell;
- wherein said well region of said access transistor is electrically connected to said buried layer region;
- wherein said depletion region is formed as a result of an application of said back bias to said buried layer region;
- and
- a control circuit to access said semiconductor memory cells.
13 more elements
An integrated circuit comprising:
- a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
- a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- a first insulating region located above said floating body region;
- second insulating regions adjacent to said floating body region on opposite sides of said floating body region;
- a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region;
- an access transistor, wherein said access transistor comprises said well region;
- and
- a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;
- wherein said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and a depletion region formed as a result of an application of a back bias to said well region;
- wherein said well region of said access transistor is electrically connected to said buried layer region;
- and
- a control circuit to access said semiconductor memory cells.
12 more elements
Dependencies are inferred from the claim text.