Asynchronous analog-to-digital converter
AssigneeTexas Instruments Incorporated
InventorsRajashekar Goroju, Prasanth K, Dileepkumar Ramesh Bhat, Rahul Sharma
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Abstract
An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.
Claims20
An integrated circuit, comprising:
- a comparator having an enable signal input and an output;
- and
- timing circuitry including:
- a first transistor having a control terminal;
- a second transistor having a control terminal;
- a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input;
- and
- a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.
An integrated circuit, comprising:
- a comparator having a signal input, an enable signal input, and a ready condition output;
- a digital-to-analog converter having a threshold voltage generation input and at least one output coupled to the signal input;
- and
- timing circuitry coupled to the enable signal input, the timing circuitry operable to successively assert an enable signal to the enable signal input irrespective of a time that a ready signal is de-asserted active from the condition output.
An analog-to-digital converter on an integrated circuit, comprising:
- an input terminal adapted to receive an input voltage;
- a sample and hold circuit having an input and an output, the input of the sample and hold circuit coupled to the input terminal;
- a threshold and compare circuit having an input coupled to the output of the sample and hold circuit, and including:
- a comparator having an enable signal input and an output;
- and
- timing circuitry including:
- a first transistor having a control terminal;
- a second transistor having a control terminal;
- a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input;
- and
- a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.
Dependencies are inferred from the claim text.