Full adder circuit and multi-bit full adder
AssigneeZhejiang Lab
InventorsJiani GU, Xiao YU
Life of this patent
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Abstract
The present application discloses a full adder circuit and a multi-bit full adder. In the full adder circuit, an in-memory computing field-effect transistor stores data and performs logic operation on the data in the transistor and the loaded data according to different input signals; and a low-area full adder circuit is realized with very few transistors through the characteristics and the reading and writing modes of the in-memory computing field-effect transistor. The full adder circuit has a simple structure, which is greatly reduces the area and complexity of the full adder circuit, and saves 19 transistors compared with the traditional CMOS full adder circuits.
Claims9
A low-area full adder circuit based on nonvolatile in-memory computing field-effect transistors, comprising:
- a sum generating circuit comprising six in-memory computing field-effect transistors, wherein the sum generating circuit is configured to receive a first input signal, a second input signal and a third input signal, and output a first output signal;
- and
- a carry generating circuit coupled to the sum generating circuit and comprising three in-memory computing field-effect transistors, wherein the carry generating circuit is configured to receive the first input signal and the second input signal from the sum generating circuit, receive the third input signal, and output a second output signal;
- wherein the first output signal is a result of a summation logic operation of the first input signal, the second input signal and the third input signal, and the second output signal is a result of a carry logic operation of the first input signal, the second input signal and the third input signal.
Dependencies are inferred from the claim text.