Merging bit-mask atomics to the same dword
AssigneeIntel Corporation
InventorsJoydeep Ray, Abhishek R. Appu, Prathamesh Raghunath Shinde
Life of this patent
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Abstract
Embodiments described herein provide a technique to improve the performance of bit-wise atomic writes to the same double word address. One embodiment provides a graphics processor comprising a system interface, a graphics processor core coupled with the system interface, and circuitry to process memory access messages received from the graphics processor core. To process the memory access messages, the circuitry is configured to merge operands associated with one or more memory access messages to perform a bitwise atomic operation, the one or more memory access messages having addresses within a same 4-byte location in memory.
Claims20
A graphics processor comprising:
- a system interface;
- a graphics processor core coupled with the system interface;
- and
- circuitry to process memory access messages received from the graphics processor core, the circuitry configured, to process the memory access messages, to merge operands associated with one or more memory access messages to perform a bitwise atomic operation, the one or more memory access messages having addresses within a same 4-byte location in memory.
A method comprising:
- receiving a first request to perform a bitwise atomic operation on an address in memory of a graphics processor;
- receiving a second request to perform the bitwise atomic operation on a second address in the memory of the graphics processor;
- determining that the first address and the second address are within a same 4-byte location in memory;
- perform the bitwise atomic operation on an operand of the first request and the operand of the second request to generate a merged operand;
- and
- submit a memory access message to the memory of the graphics processor, the memory access message including the merged operand.
A system comprising:
- a memory device;
- and
- a graphics processor coupled with the memory device, the graphics processor including:
- a graphics processor core;
- and
- circuitry to process memory access messages received from the graphics processor core, wherein to process the memory access messages, the circuitry configured to merge operands associated with one or more memory access messages to perform a bitwise atomic operation, the one or more memory access messages having addresses within a same 4-byte location in memory.
Dependencies are inferred from the claim text.