Interleave circuit and communication device
AssigneeKabushiki Kaisha Toshiba
InventorsYutaro ISHIGAKI, Kazuaki DOI
Life of this patent
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Abstract
According to an embodiment, an interleave circuit includes a reordering circuit and an address calculation circuit. The reordering circuit is configured to, for each cycle, receive in parallel input data containing n (n is an integer of 2 or more) bits, and reorder n-pieces of the input data input in n cycles into n-pieces of output data each containing n bits input in cycles different from each other. The address calculation circuit is configured to calculate write addresses for writing the n-pieces of output data into a first storage device and read addresses for reading out the n-pieces of output data from the first storage device.
Claims7
An interleave circuit comprising:
- a reordering circuit configured to, for each cycle, receive in parallel input data containing n (n is an integer of 2 or more) bits, and reorder n-pieces of the input data input in n cycles into n-pieces of output data each containing n bits input in cycles different from each other;
- and
- an address calculation circuit configured to calculate write addresses for writing the n-pieces of output data into a first storage device and read addresses for reading out the n-pieces of output data from the first storage device.
A communication device comprising:
- an interleave circuit outputting output data that is reordered from input data;
- and
- a processor configured to execute error correction on the output data,
- the interleave circuit comprising:
- a reordering circuit configured to, for each cycle, receive in parallel input data containing n (n is an integer of 2 or more) bits, and reorder n-pieces of the input data input in n cycles into n-pieces of the output data each containing n bits input in cycles different from each other;
- and
- an address calculation circuit configured to calculate write addresses for writing the n-pieces of output data into a first storage device and read addresses for reading out the n-pieces of output data from the first storage device.
Dependencies are inferred from the claim text.