Memory controller and method for bit flipping of low-density parity-check codes

A method for bit flipping of low-density parity check (LDPC) codes, for use in a memory controller of a data storage device, wherein the memory controller comprises a variable-node circuit and a check-node circuit, the method comprising:

• storing data in the flash memory of the data storage device via a storage program;
• obtaining a channel value read from the flash memory of the data storage device;
• obtaining a codeword difference, and calculating a syndrome according to the codeword difference,
• utilizing a threshold-tracking circuit in the memory controller to track a threshold used by the variable-node circuit during an LDPC decoding process to determine whether the variable-node circuit has entered a trapping status;
• and
• in response to determining that the variable-node circuit has entered the trapping status during the LDPC decoding process, switching a bit-flipping algorithm used by the memory controller during the LDPC decoding process from a first flipping strategy to a post-processing flipping strategy to bring the variable-node circuit out of the trapping status,
• wherein the first flipping strategy is different from the post-processing flipping strategy.