Programmable capacitor memory arrays with stacked access transistors
AssigneeIntel Corporation
InventorsAbhishek Anil Sharma, Tahir Ghani, Anand Murthy, Wilfred Gomes
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Abstract
Bits are stored in an array with multiple capacitors per access transistor. An array of multiple ferroelectric capacitors shares a nanowire or nanosheet as a common plate and stores information accessed by a single common select transistor, which uses the nanowire or nanosheet for its channel. In an integrated circuit (IC) system, a group of bitlines is connected to a capacitor array by arrays of nanowires or nanosheets and wordline-controlled non-planar transistors. An IC die with a capacitor array accessed by a single select transistor and sharing a nanowire or nanosheet is coupled to a power supply and a cooling structure.
Claims23
A memory device, comprising:
- a nanowire or nanosheet comprising a channel region and a common capacitor plate region;
- a plurality of capacitors, wherein individual ones of the capacitors comprise a portion of the common capacitor plate region of the nanowire or nanosheet, a ferroelectric layer, and an independent second capacitor plate;
- and
- a non-planar transistor comprising the channel region of the nanowire or nanosheet and a gate electrode.
An integrated circuit (IC) system, comprising:
- an array of nanowires or nanosheets, wherein individual ones of the nanowires or nanosheets comprise a transistor channel and a first capacitor plate;
- an array of gate structures, wherein individual ones of the gate structures are in contact with corresponding ones of the transistor channels;
- a plurality of bitlines extending in a first direction, wherein individual ones of the bitlines are coupled to first ends of the transistor channels, and second ends of the transistor channels are coupled to corresponding ones of the first capacitor plates;
- a plurality of wordlines extending in a second direction substantially orthogonal to the first direction, wherein individual ones of the wordlines are coupled to the gate structures;
- and
- an array of capacitors, wherein individual ones of the capacitors comprise a portion of corresponding ones of the first capacitor plates, a second capacitor plate, and a ferroelectric material therebetween.
An integrated circuit (IC) system, comprising:
- a power supply;
- and
- an IC die coupled to the power supply, the IC die comprising:
- a plurality of capacitors comprising a shared inner plate, wherein individual ones of the capacitors comprise an outer plate and a ferroelectric material between the shared inner plate and the outer plate;
- a transistor comprising a channel portion;
- and
- a nanowire or nanosheet comprising the channel portion and the shared inner plate.
Dependencies are inferred from the claim text.