Nor-type memory device, method of manufacturing nor-type memory device, and electronic apparatus including memory device

A NOR-type memory device, comprising:

• at least one memory cell layer disposed on a substrate, wherein the at least one memory cell layer comprises a first source/drain layer, a first channel layer, a second source/drain layer, a second channel layer, and a third source/drain layer which are stacked in a vertical direction;
• at least one gate stack that extends vertically with respect to the substrate to pass through the at least one memory cell layer, wherein the at least one gate stack comprises a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the at least one memory cell layer, and a memory cell is defined at an intersection of the at least one gate stack and the at least one memory cell layer;
• and
• at least one of a source line contact portion and a bulk contact portion,
• wherein the source line contact portion extends vertically with respect to the substrate to pass through the at least one memory cell layer, wherein at a position where the source line contact portion is located, the first source/drain layer and the third source/drain layer in the at least one memory cell layer are electrically connected to the source line contact portion respectively, and
• wherein the bulk contact portion extends vertically with respect to the substrate to pass through the at least one memory cell layer, wherein at a position where the bulk contact portion is located, the first channel layer and the second channel layer in the at least one memory cell layer are electrically connected to the bulk contact portion respectively.