Integrated circuit structures having vertical transistor

An integrated circuit structure, comprising:

• a front-side structure comprising:
• a device layer having a plurality of fin-based transistors;
• and
• a plurality of metallization layers above the fin-based transistors of the device layer;
• a backside structure below the fin-based transistors of the device layer, the backside structure including a ground metal line;
• and
• one or more vertical transistors between the fin-based transistors of the device layer and the ground metal line of the backside structure, each of the vertical transistors including a channel structure on a drain contact layer, the channel structure having an opening extending there through, a gate dielectric layer on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure, a gate electrode on and laterally surrounded by the gate dielectric layer, and a source contact layer on sides of a portion of the gate dielectric layer extending above the channel structure.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a channel structure on a drain contact layer, the channel structure having an opening extending there through;
• a gate dielectric layer on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure;
• a gate electrode on and laterally surrounded by the gate dielectric layer;
• and a source contact layer on sides of a portion of the gate dielectric layer extending above the channel structure.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a front-side structure comprising:
• a device layer having a plurality of fin-based transistors;
• and
• a plurality of metallization layers above the fin-based transistors of the device layer;
• a backside structure below the fin-based transistors of the device layer, the backside structure including a ground metal line;
• and
• one or more vertical transistors between the fin-based transistors of the device layer and the ground metal line of the backside structure, each of the vertical transistors including a channel structure on a drain contact layer, the channel structure having an opening extending there through, a gate dielectric layer on a bottom and along sides of the opening, the gate dielectric layer laterally surrounded by the channel structure, a gate electrode on and laterally surrounded by the gate dielectric layer, and a source contact layer on sides of a portion of the gate dielectric layer extending above the channel structure.