Chip package structure having molding layer

A chip package structure, comprising:

• a first redistribution structure having a first surface and a second surface opposite to the first surface;
• a first chip over the first surface;
• a first conductive pillar over the first surface and adjacent to the first chip;
• a second chip over the second surface;
• a second conductive pillar over the second surface and adjacent to the second chip;
• a first molding layer over the first surface and surrounding the first chip, wherein the first conductive pillar passes through the first molding layer, a first portion of the first molding layer covers a first bottom surface of the first chip, and the first bottom surface faces away from the first redistribution structure;
• and
• a second molding layer over the second surface and surrounding the second chip, wherein the second conductive pillar passes through the second molding layer, a second portion of the second molding layer covers a first top surface of the second chip, the first top surface faces away from the first redistribution structure, and
• the first chip, the first redistribution structure, and the second chip are between the first portion of the first molding layer and the second portion of the second molding layer.