US 2024/0006325 A1 · METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

Claims20

Dependent claims

A method of fabricating a semiconductor package, the method comprising:

forming an interposer chip that includes a base layer, a redistribution layer on a first surface of the base layer, and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed on a second surface of the base layer;
providing the interposer chip into a core portion that includes a conductive element;
forming a first buildup portion on a top surface of the core portion and the first surface of the base layer, the first buildup portion being connected to the conductive element and the redistribution layer;
forming a second buildup portion on a bottom surface of the core portion and the second surface of the base layer, the second buildup portion being connected to the conductive element and the via;
mounting a plurality of semiconductor chips on the first buildup portion;
and
forming on the first buildup portion a molding layer that covers the plurality of semiconductor chips,
wherein the plurality of semiconductor chips are electrically connected to each other through the first buildup portion and the interposer chip.

5 more elements

A method of fabricating a semiconductor package, the method comprising:

forming an interposer chip that includes a base layer, a redistribution layer on a first surface of the base layer, and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed on a second surface of the base layer;
forming an embedding region in a core portion;
providing the interposer chip into the embedding region in the core portion;
forming a first buildup portion on a top surface of the core portion and a top surface of interposer chip, the first buildup portion being connected to the core portion and the redistribution layer;
forming a second buildup portion on a bottom surface of the core portion and the second surface of the base layer, the second buildup portion being connected to the core portion and the via;
mounting a plurality of semiconductor chips on the first buildup portion;
and
forming on the first buildup portion a molding layer that covers the plurality of semiconductor chips,
wherein a top surface of the via is located at a same level as a level of the first surface of the base layer, and
wherein a top surface of the redistribution layer of the interposer chip is located at a same level as a level of the top surface of the core portion, and the top surface of the redistribution layer of the interposer chip is in contact with the first buildup portion.

7 more elements

Dependencies are inferred from the claim text.

Method of fabricating a semiconductor package

Life of this patent

Method of fabricating a semiconductor package

Life of this patent

Abstract

Claims20