Power rail and signal line arrangement in integrated circuits having stacked transistors

A method comprising:

• fabricating a first-type active-region semiconductor structure extending in a first direction on a substrate;
• fabricating a first source conductive segment intersecting the first-type active-region semiconductor structure at a first source region;
• depositing a layer of dielectric material covering at least the first-type active-region semiconductor structure;
• fabricating a second-type active-region semiconductor structure extending in the first direction atop the layer of dielectric material, wherein the second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure;
• fabricating a second source conductive segment intersecting the second-type active-region semiconductor structure at a second source region;
• depositing a first insulating material covering the second source conductive segment;
• forming a first via-connector connecting to the second source conductive segment and passing through the first insulating material;
• depositing a front-side metal layer over the first insulating material and patterning the front-side metal layer to form a front-side power rail extending in the first direction and a front-side signal line extending in the first direction, wherein the front-side power rail is conductively connected to the first via-connector;
• forming a second via-connector connecting to the first source conductive segment and passing through the substrate;
• and
• forming a back-side metal layer on a backside of the substrate and patterning the back side metal layer to form a back-side power rail extending in the first direction and a back-side signal line extending in the first direction, wherein the back-side power rail is conductively connected to the second via-connector.

A method comprising:

• fabricating a first-type active-region semiconductor structure extending in a first direction on a substrate;
• depositing a layer of dielectric material covering at least the first-type active-region semiconductor structure;
• fabricating a second-type active-region semiconductor structure extending in the first direction atop the layer of dielectric material, wherein the second-type active-region semiconductor structure is stacked with the first-type active-region semiconductor structure;
• depositing a first insulating material covering at least the second-type active-region semiconductor structure;
• forming a first via-connector passing through the first insulating material and connecting to a source terminal of a first second-type transistor in the second-type active-region semiconductor structure;
• depositing a front-side metal layer over the first insulating material and patterning the front-side metal layer to form a front-side power rail extending in the first direction and a front-side signal line extending in the first direction, wherein the front-side power rail is conductively connected to the first via-connector;
• forming a second via-connector passing through the substrate and connecting to a source terminal of a first first-type transistor in the first-type active-region semiconductor structure;
• and
• forming a back-side metal layer on a backside of the substrate and patterning the back side metal layer to form a back-side power rail extending in the first direction and a back-side signal line extending in the first direction, wherein the back-side power rail is conductively connected to the second via-connector.