Semiconductor package
AssigneesnD-HI Technologies Lab, Inc., Etron Technology, Inc.
InventorsHO-MING TONG, CHAO-CHUN LU
Life of this patent
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Abstract
A semiconductor package is provided. The semiconductor package includes an integrated circuit (IC) block and a first substrate. The IC block has a first interconnect layer. The first substrate carries the IC block. The first substrate includes a second interconnect layer facing the first interconnect layer and a third interconnect layer opposite to the second interconnect layer. Furthermore, at least one of the second interconnect layer or the third interconnect layer is composed of a dielectric material and a conductive material substantially identical to a corresponding dielectric material and a corresponding conductive material of the first interconnect layer.
Claims20
A semiconductor package, comprising:
- an integrated circuit (IC) block having a first interconnect layer;
- and
- a first substrate carrying the IC block, comprising:
- a second interconnect layer facing the first interconnect layer;
- and
- a third interconnect layer opposite to the second interconnect layer,
- wherein at least one of the second interconnect layer or the third interconnect layer is composed of a dielectric material and a conductive material substantially identical to a corresponding dielectric material and a corresponding conductive material of the first interconnect layer.
A semiconductor package, comprising:
- a first substrate, including:
- a first interconnect layer configured for hybrid bonding to an integrated circuit (IC) block or a second substrate with the first interconnect layer comprising a first dielectric and a first line width;
- and
- a second interconnect layer opposite to the first interconnect layer with the second interconnect layer comprising a second dielectric and a second line width,
- wherein the first dielectric is identical to or different from the second dielectric, and the first line width is identical to or different from the second line width.
A semiconductor package, comprising:
- a first substrate, comprising:
- a pre-preg wiring layer having a minimal line width/line spacing (L/S) greater than 10 μm/10 μm;
- a first build-up wiring layer over a top surface of the pre-preg wiring layer, having a minimal L/S between 6 μm/6 μm and 10 μm/10 μm;
- and
- a first repassivation wiring layer over a top surface of the first build-up wiring layer, having a minimal L/S equal to or smaller than 2 μm/2 μm,
- wherein the first repassivation wiring layer is composed of a polyimide or an oxide, forming a first interconnect layer configured to bond to an integrated circuit (IC) block or another substrate.
Dependencies are inferred from the claim text.