Pocketed copper in first layer interconnect and method
AssigneeIntel Corporation
InventorsSuddhasattwa Nad, Jeremy D. Ecton, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jason Steill, Yi Yang, Marcel Arlan Wall
Life of this patent
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Abstract
A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.
Claims20
A substrate package comprising:
- a substrate comprised of buildup layers;
- a layer connected to the substrate and including a pocketed region, the layer including silicon and nitrogen, the pocketed region including a first portion thinner than a second portion extending from the first portion;
- and
- a solder ball encapsulated within the pocketed region.
An electronic device comprising:
- a substrate package comprising:
- a substrate comprised of buildup layers;
- a passivating layer connected to the substrate and including a pocketed region, the pocketed region including a first portion thinner than a second portion extending from the first portion;
- a solder ball encapsulated within the pocketed region;
- and
- an integrated circuit mounted to the substrate package.
A method of manufacture of a substrate package, the method comprising:
- forming a substrate comprised of buildup layers;
- forming a passivating layer connected to the substrate and including a pocketed region, the pocketed region including a first portion thinner than a second portion extending from the first portion;
- and
- encapsulating a solder ball within the pocketed region.
Dependencies are inferred from the claim text.