A processor architecture arrangement for an emulated shared memory (ESM) architecture, the processor architecture arrangement comprising:
- a number of multi-threaded processors each provided with an interleaved inter-thread pipeline, multiple threads being executed in cyclic, interleaved manner by each pipeline so that a number of other threads are executed while a thread references a common physically distributed and logically shared data memory of the ESM architecture, and a plurality of functional units for carrying out arithmetic and logical operations on data,
- wherein each interleaved inter-thread pipeline includes at least two operatively parallel pipeline branches, a first pipeline branch having a first sub-group of said plurality of functional units which are configured to and arranged for carrying out integer operations, and a second pipeline branch having a second, non-overlapping, sub-group of said plurality of functional units which are configured to and arranged for carrying out floating point operations, and wherein the first and the second pipeline branches each comprise a plurality of segments, the segments being connected in series, and wherein each segment comprises one or more of said functional units, wherein the plurality of segments of the first and second pipeline branches are parallel with each other such that parallel segments of the first and second pipeline branches begin after a same latency from a beginning of the interleaved inter-thread pipeline,
- wherein at least one of the functional units of the second sub-group which is configured to and arranged for performing floating point operations is located operatively in parallel with a memory access segment and operates concurrently with the memory access segment after a same latency from the beginning of the interleaved inter-thread pipeline, such that pipeline stages of associated floating-point operations are executed simultaneously with parallel pipeline stages of a memory unit taking care of pending access of shared data memory, while pipeline stages of a first segment of floating point functional units are operated in parallel with corresponding stages of a first segment of arithmetic and logic functional units and pipeline stages of a second segment of floating point functional units are operating in parallel with corresponding stages of a second segment of arithmetic and logic functional units, and wherein no overlapping exists between the functional units included in the first sub-group and the functional units included in the second sub-group, and wherein at least one of the floating point functional has a longer execution latency than at least one of the integer units.