Memory Circuitry And Method Used In Forming Memory Circuitry

Memory circuitry, comprising:

• a substrate comprising transistors individually comprising:
• a pair of source/drain regions;
• a channel region between the pair of source/drain regions;
• and
• a conductive gate operatively proximate the channel region;
• conductor vias that are individually directly electrically coupled to one of the source/drain regions of the pair of source/drain regions;
• conductive vias that are individually directly electrically coupled to the other of the source/drain regions of the pair of source/drain regions;
• digitlines that are individually directly electrically coupled to a plurality of the conductive vias along a line of multiple of the transistors, the digitlines in a vertical cross-section individually having two sidewalls that taper laterally-inward from top-to-bottom;
• and
• a storage element directly electrically coupled to individual of the conductor vias.

Memory circuitry, comprising:

• a substrate comprising transistors individually comprising:
• a pair of source/drain regions;
• a channel region between the pair of source/drain regions;
• and
• a conductive gate operatively proximate the channel region;
• conductor vias that are individually directly electrically coupled to one of the source/drain regions of the pair of source/drain regions;
• conductive vias that are individually directly electrically coupled to the other of the source/drain regions of the pair of source/drain regions;
• digitlines that are individually directly electrically coupled to a plurality of the conductive vias along a line of multiple of the transistors;
• the conductor vias individually comprising:
• lower conductively-doped semiconductive material directly electrically coupled to the one source/drain region;
• and
• upper metal material directly above and directly electrically coupled to the lower conductively-doped semiconductive material, the upper metal material covering all of a top surface of the lower conductively-doped semiconductive material;
• and
• a storage element directly electrically coupled to the upper metal material of individual of the conductor vias.

Memory circuitry, comprising:

• a substrate comprising transistors individually comprising:
• a pair of source/drain regions;
• a channel region between the pair of source/drain regions;
• and
• a conductive gate operatively proximate the channel region;
• conductor vias that are individually directly electrically coupled to one of the source/drain regions of the pair of source/drain regions;
• conductive vias that are individually directly electrically coupled to the other of the source/drain regions of the pair of source/drain regions;
• digitlines that are individually directly electrically coupled to a plurality of the conductive vias along a line of multiple of the transistors;
• a storage element directly electrically coupled to individual of the conductor vias;
• and
• the conductor vias individually comprising a portion that is directly under one of the digitlines.