High flux led with low operating voltage utilizing two p-n junctions connected in parallel and having one tunnel junction
AssigneeLumileds LLC
InventorRobert Armitage
Life of this patent
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Abstract
Provided is an LED comprised of a first and a second p-n junction deposited sequentially on the same wafer. The first and second junctions have opposite orders of deposition of the n- and p-layers. One light-emitting active region is embedded between the n- and p-layers of the first junction and another light-emitting active region is embedded between the n- and p-layers of the second junction. Contacts are processed such that forward current can be passed in parallel through both of the junctions using a single voltage source. For a given forward current, the LED operates at lower voltage with higher optical flux and efficiency.
Claims20
A light-emitting diode (LED) die comprising:
- a first light emitting stack on a second light emitting stack, wherein
- the first light emitting stack comprises a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light-emitting active region,
- the second light emitting stack comprises a second n-type layer in contact with the first light-emitting active region and on a second light-emitting active region, the second light-emitting active region on a second p-type layer;
- and
- a metal contact on the second light emitting stack and extending to the first light emitting stack.
A method of manufacturing a light-emitting diode (LED) die, the method comprising:
- epitaxially growing a first light emitting stack and a second light emitting stack on an epitaxial wafer, the first light emitting stack comprising a first n-type layer on a first tunnel junction, the first tunnel junction on a first p-type layer, and the first p-type layer on a first light-emitting active region, the second light emitting stack comprising a second n-type layer in contact with the first light-emitting active region and on a second light-emitting active region, the second light-emitting active region on a second p-type layer;
- and
- forming at least one metal contact on the second light emitting stack.
A method of manufacturing thin film flip chip (TFFC) die, the method comprising:
- sequentially forming two p-n junctions on an epitaxial wafer to form an epitaxial stack, the epitaxial stack comprising at least one n-type layer and at least one p-type layer and having a light-emitting active region embedded between the at least one n-type layer and at least one p-type layer;
- dry etching the epitaxial stack to form two vias of different depths;
- conformally depositing a dielectric layer in the two vias;
- removing a portion of the dielectric layer to form contact openings;
- depositing one or more of an anode layer and a cathode layer in the contact openings;
- depositing a bonding metal layer on one or more of the anode layer or the cathode layer;
- singulating the thin film flip chip (TFFC) die;
- and
- bonding the thin film flip chip (TFFC) die to a sub-mount.
Dependencies are inferred from the claim text.