Semiconductor device with reverse-cut source/drain contact structure and method thereof

A method, comprising:

• providing a structure having semiconductor fins, an isolation structure adjacent to lower portions of the semiconductor fins, source/drain electrodes over the semiconductor fins, gate structures over channel regions of the semiconductor fins, a first etch stop layer on the source/drain electrodes, the isolation structure, and the gate structures, a first interlayer dielectric layer on the first etch stop layer, a second etch stop layer on the gate structures, the first etch stop layer, and the first interlayer dielectric layer, and a second interlayer dielectric layer on the second etch stop layer;
• forming a first etch mask that provides first openings over the second interlayer dielectric layer;
• performing a first etching to at least the second interlayer dielectric layer, the second etch stop layer, and the first interlayer dielectric layer through the first openings, resulting in first trenches;
• filling the first trenches with one or more third dielectric layers that have a different material than the second interlayer dielectric layer;
• forming a second etch mask that provides second openings directly above the second interlayer dielectric layer and the one or more third dielectric layers;
• performing a second etching to at least the second interlayer dielectric layer, the second etch stop layer, the first interlayer dielectric layer, and the first etch stop layer through the second openings, resulting in second trenches that expose some of the source/drain electrodes, wherein the second etching is tuned not to etch the one or more third dielectric layers;
• and
• forming source/drain contact plugs in the second trenches.

A semiconductor structure, comprising:

• gate structures;
• source/drain electrodes adjacent to the gate structures;
• a first etch stop layer over the source/drain electrodes and the gate structures;
• a first interlayer dielectric layer over the first etch stop layer;
• a second etch stop layer over the gate structures, the first etch stop layer, and the first interlayer dielectric layer;
• a second interlayer dielectric layer over the second etch stop layer;
• first dielectric structures disposed between adjacent ones of the gate structures from a top view and extending vertically from a top surface of the second interlayer dielectric layer to a point within or below the first interlayer dielectric layer;
• and
• source/drain contacts extending through the first and the second interlayer dielectric layers and the first and the second etch stop layers and landing on some of the source/drain electrodes.