Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate that includes an active pattern;
• a channel pattern disposed on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns that are stacked on each other and spaced apart from each other;
• a source/drain pattern connected to the plurality of semiconductor patterns;
• a gate electrode that covers the plurality of semiconductor patterns;
• a gate dielectric layer disposed between the plurality of semiconductor patterns and the gate electrode;
• and
• a lower dielectric pattern disposed between the active pattern and the gate electrode,
• wherein the gate dielectric layer covers at least a portion of a top surface of the lower dielectric pattern, and
• wherein the lower dielectric pattern and the gate electrode are spaced apart from each with the gate dielectric layer disposed therebetween.

A semiconductor device, comprising:

• a substrate that includes an active region;
• a device isolation layer that defines an active pattern on the active region;
• a lower dielectric pattern disposed on the active pattern;
• a channel pattern disposed on the lower dielectric pattern;
• a source/drain pattern disposed on a first surface of the channel pattern, wherein the source/drain pattern penetrates the lower dielectric pattern;
• a gate electrode disposed on the channel pattern;
• a gate dielectric layer disposed between the gate electrode and the channel pattern;
• a gate spacer disposed on a sidewall of the gate electrode;
• a gate capping pattern disposed on the gate electrode;
• an interlayer dielectric layer disposed on the gate capping pattern;
• an active contact that penetrates the interlayer dielectric layer and is electrically connected with the source/drain pattern;
• a metal-semiconductor compound layer disposed between the active contact and the source/drain pattern;
• a gate contact that penetrates the interlayer dielectric layer and the gate capping pattern and is electrically connected with the gate electrode;
• a first metal layer disposed on the interlayer dielectric layer, wherein the first metal layer includes a power line and first wiring lines, wherein the first wiring lines are correspondingly electrically connected to the active contact and the gate contact;
• and
• a second metal layer disposed on the first metal layer,
• wherein the second metal layer includes second wiring lines electrically connected to the first metal layer,
• wherein the channel pattern includes a plurality of semiconductor patterns that are stacked in a second direction substantially perpendicular to a top surface of the substrate,
• wherein the gate dielectric layer includes an interface layer and a high-k dielectric layer, wherein the interface layer covers the semiconductor patterns, and the high-k dielectric layer is disposed on the interface layer, and
• wherein the lower dielectric pattern and the interface layer include different materials from each other.