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US 2023/0420546 A1Published application
Transistor with current terminal regions and channel region in layer over dielectric
AssigneeNXP USA, Inc.
InventorsPetrus Hubertus Cornelis Magnee, Jay Paul John
Life of this patent
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Abstract
A method includes making a semiconductor die that includes a transistor with a control terminal, and two current terminals. The two current terminals include portions located in a semiconductor layer formed by an epitaxial process on a substrate with semiconductor material and dielectric material. At least some of the portions of the current terminals located in the semiconductor layer are characterized as monocrystalline and are located directly over dielectric material of the substrate. The channel region is located in a monocrystalline portion of the semiconductor layer as well.
Claims20
A method for forming a semiconductor die including a transistor, the method comprising:
- on a wafer including a substrate with semiconductor material and dielectric material wherein the dielectric material of the substrate defines an opening on a surface of the substrate with exposed semiconductor material, forming an epitaxially grown semiconductor layer on the substrate, the epitaxially grown semiconductor layer includes a monocrystalline portion located directly over the opening and extending laterally across the opening to locations located directly over the dielectric material;
- forming a control terminal for a transistor including a portion located directly over the monocrystalline portion of the epitaxially grown semiconductor layer;
- forming a first current terminal region of the transistor in the epitaxially grown semiconductor layer, wherein at least a portion of the first current terminal region is located in the monocrystalline portion located directly over the dielectric material,
- forming a second current terminal region of the transistor in the epitaxially grown semiconductor layer, wherein at least a portion of the second current terminal region is located in the monocrystalline portion located directly over the dielectric material, wherein the monocrystalline portion of the epitaxially grown semiconductor layer includes a channel region extending between the first current terminal region and the second current terminal region and directly beneath the control terminal;
- separating the wafer into a plurality of die including a first die, wherein the first die includes the transistor.
2 more elements
A method for forming a semiconductor die including a transistor, the method comprising:
- forming a layer of semiconductor material by an epitaxial process on a substrate of a wafer where semiconductor material of the layer formed on a monocrystalline portion of the substrate has a monocrystalline structure and semiconductor material of the layer formed on dielectric material of the substrate has a non monocrystalline structure;
- after the forming the layer, converting portions of the layer having a non monocrystalline structure to having a monocrystalline structure;
- forming a control terminal of a transistor directly over the layer;
- forming a first current terminal region of the transistor in the layer including in a portion of the layer that was converted from having a non monocrystalline structure to having mono crystalline structure;
- forming a second current terminal region of the transistor in the layer including in a portion of the layer that was converted from having a non monocrystalline structure to having monocrystalline structure, wherein a portion of the layer having a monocrystalline structure includes a channel region that extends in the layer from the first current terminal region to the second current terminal region;
- separating the wafer into a plurality of die including a first die, wherein the first die includes the transistor.
3 more elements
A method for forming a semiconductor die including a transistor, the method comprising:
- on a wafer including a substrate with semiconductor material and dielectric material, wherein the dielectric material of the substrate defines an opening on a surface of the substrate with exposed semiconductor material, forming a semiconductor structure over the substrate, the semiconductor structure includes a monocrystalline portion located directly over the opening, the monocrystalline portion extends to at least a portion of a first patterned lateral edge of the semiconductor structure located over the dielectric material and to at least a portion of a second patterned lateral edge of the semiconductor structure located over the dielectric material, the first patterned lateral edge being an opposite lateral edge to the second patterned lateral edge of the semiconductor structure, the semiconductor structure is formed by patterning an epitaxially grown semiconductor layer on the substrate;
- forming a control terminal for a transistor over the semiconductor structure, the control terminal located directly over the portion of the first patterned lateral edge and the portion of the second patterned lateral edge;
- forming a first current terminal region of the transistor in the semiconductor structure, the forming the first current terminal region includes implanting conductivity dopants into a third portion of the semiconductor structure not covered by the control terminal;
- forming a second current terminal region of the transistor in the semiconductor structure, the forming the second current terminal region includes implanting conductivity dopants into a fourth portion of the semiconductor structure not covered by the control terminal, wherein the monocrystalline portion of the semiconductor structure includes a channel region extending between the first current terminal region and the second current terminal region in the monocrystalline portion and directly beneath the control terminal;
- separating the wafer into a plurality of die including a first die, wherein the first die includes the transistor.
2 more elements
Dependencies are inferred from the claim text.