Gate cut and fin trim isolation for advanced integrated circuit structure fabrication

An integrated circuit structure, comprising:

• a first fin continuous with an underlying substrate;
• a second fin continuous with the underlying substrate, the second fin laterally spaced apart from the first fin;
• a cut in the underlying substrate, the cut between the first fin and the second fin;
• a dielectric plug laterally between the first fin and the second fin, the dielectric plug in the cut, and the dielectric plug extending from a level below a bottom of the first fin and the second fin to a level above a top of the first fin and the second fin, the dielectric plug having an uppermost surface;
• a first gate electrode over the first fin, the first gate electrode having an uppermost surface at a same level as the uppermost surface of the dielectric plug;
• and
• a second gate electrode over the second fin, the second gate electrode having an uppermost surface at a same level as the uppermost surface of the dielectric plug.

An integrated circuit structure, comprising:

• a first fin continuous with an underlying substrate;
• a second fin continuous with the underlying substrate, the second fin laterally spaced apart from the first fin;
• a cut in the underlying substrate, the cut between the first fin and the second fin;
• a dielectric plug laterally between the first fin and the second fin, the dielectric plug extending into the cut, and the dielectric plug having a bottommost surface below a bottom of the first fin and the second fin;
• a first gate electrode over the first fin, the first gate electrode having an uppermost surface at a same level as the uppermost surface of the dielectric plug;
• and
• a second gate electrode over the second fin, the second gate electrode having an uppermost surface at a same level as the uppermost surface of the dielectric plug.

An integrated circuit structure, comprising:

• a first discrete three-dimensional body above an underlying substrate, the first discrete three-dimensional body having a channel region;
• a second discrete three-dimensional body above the underlying substrate, the second discrete three-dimensional body laterally spaced apart from the first discrete three-dimensional body, and the second discrete three-dimensional body having a channel region;
• a cut in the underlying substrate, the cut between the first discrete three-dimensional body and the second discrete three-dimensional body;
• a dielectric plug laterally between the first discrete three-dimensional body and the second discrete three-dimensional body, the dielectric plug in the cut, and the dielectric plug extending from a level below a bottom of the first discrete three-dimensional body and the second discrete three-dimensional body to a level above a top of the first discrete three-dimensional body and the second discrete three-dimensional body, the dielectric plug having an uppermost surface;
• a first gate electrode completely surrounding the channel region of the first discrete three-dimensional body, the first gate electrode having an uppermost surface at a same level as the uppermost surface of the dielectric plug;
• and
• a second gate electrode completely surrounding the channel region of the second discrete three-dimensional body, the second gate electrode having an uppermost surface at a same level as the uppermost surface of the dielectric plug.