US 2023/0420535 A1Published application

Semiconductor devices

AssigneeSamsung Electronics Co., Ltd.

InventorsKanghun Moon, Kyungho Kim, Kihwan Kim, Choeun Lee, Yonguk Jeon

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Abstract

A semiconductor device includes: an active region on a substrate extending in a first direction; a plurality of semiconductor layers spaced apart from each in a vertical direction on the active region, the plurality of semiconductor layers including lower and upper semiconductor layers; a gate structure on the substrate extending in a second direction to intersect the active region and the plurality of semiconductor layers; and a source/drain region on the active region and contacting the plurality of semiconductor layers. The source/drain region includes first epitaxial layers, including first layers on a side surface of the lower semiconductor layer and a second layer provided on and contacting the active region, and a second epitaxial layer contacts a side surface of the upper semiconductor layer in the first direction, and the first layer is between the second epitaxial layer and the side surface of the lower semiconductor layer.

Claims20

Dependent claims

A semiconductor device comprising:

a substrate;
an active region extending in a first direction on the substrate;
a plurality of semiconductor layers spaced apart from each other in a vertical direction on the active region, the plurality of semiconductor layers comprising a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer;
a gate structure extending in a second direction on the substrate and intersecting the active region and the plurality of semiconductor layers, the gate structure surrounding the plurality of semiconductor layers;
and
a source/drain region provided on the active region on at least one side adjacent to the gate structure and contacting the plurality of semiconductor layers,
wherein the source/drain region comprises first epitaxial layers and a second epitaxial layer,
wherein the first epitaxial layers comprise a first layer contacting a side surface of the lower semiconductor layer in the first direction, and a second layer provided on and contacting the active region,
wherein the second epitaxial layer contacts a side surface of the upper semiconductor layer in the first direction, and
wherein the first layer is between the second epitaxial layer and the side surface of the lower semiconductor layer.

7 more elements

A semiconductor device comprising:

a substrate;
an active region extending in a first direction on the substrate;
a plurality of semiconductor layers spaced apart from each other in a vertical direction on the active region;
a gate structure extending in a second direction on the substrate and intersecting the active region and the plurality of semiconductor layers, the gate structure surrounding the plurality of semiconductor layers;
inner spacer layers provided on opposite sides adjacent to the gate structure in the first direction on a lower surface of each of the plurality of semiconductor layers and vertically overlapping the plurality of semiconductor layers;
and
a source/drain region provided on the active region on at least one side adjacent to the gate structure and contacting the plurality of semiconductor layers,
wherein the plurality of semiconductor layers comprise a lower semiconductor layer and an upper semiconductor layer provided on the lower semiconductor layer, and
wherein the source/drain region comprises:
a first epitaxial layer provided on a side surface of the lower semiconductor layer and at a level lower than a level of the upper semiconductor layer;
and
a second epitaxial layer having a composition that is different from a composition of the first epitaxial layer, extending upwardly on a side surface of the upper semiconductor layer and covering the first epitaxial layer.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/195,074Filed 9 May 2023
Priority: KR 10-2022-007692823 Jun 2022
Published: 28 Dec 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 30/6735
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having gates fully surrounding the channels, e.g. gate-all-around
H10D 30/0193
Forming stacked channels, e.g. changing their shapes or sizes: by modifying properties of the stacked channels
H10D 30/43
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having one-dimensional [1D] charge…
H10D 30/504
Characterised by the stacked channels: wherein the stacked channels have different properties