Fabrication of gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with an opposite polarity dipole layer

An integrated circuit structure, comprising:

• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having an N-type conductive layer on a first gate dielectric comprising a first P-type dipole material layer and a second P-type dipole material layer;
• and
• a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the N-type conductive layer on a second gate dielectric comprising the first P-type dipole material layer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric comprising a first N-type dipole material layer;
• and
• a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric comprising the first N-type dipole material layer and a second N-type dipole material layer.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires;
• a second vertical arrangement of horizontal nanowires;
• a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having an N-type conductive layer on a first gate dielectric comprising a first P-type dipole material layer and a second P-type dipole material layer;
• and
• a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the N-type conductive layer on a second gate dielectric comprising the first P-type dipole material layer.