Forming a forksheet nanodevice

A method comprising:

• etching a hardmask on a nanosheet stack to simultaneously form a plurality of hardmask caps over a plurality of pFET (p-doped Field Effect Transistor) and nFET (n-doped Field Effect Transistor) precursor regions, wherein spaces of varying widths separate the hardmask caps at different locations of the nanosheet stack;
• depositing spacers on the hardmask and reactive ion etching the spacers to form gaps that correspond to the spaces that were separating the hardmask caps;
• forming trenches of varying widths by etching the nanosheet stack through the gaps;
• depositing a sacrificial liner with a liner thickness on the hardmask caps and into the trenches;
• isotropically etching back the sacrificial liner so that portions of the sacrificial liner are removed from trenches that are wider than twice the liner thickness, while other portions of the sacrificial liner remain in pinch-off trenches that are narrower than twice the liner thickness;
• and
• completing a plurality of complementary metal-oxide-silicon transistors that include p-doped and n-doped source/drain structures in respective ones of the pFET and the nFET precursor regions, wherein dielectric material fills the trenches between the pFET and nFET precursor regions.

A semiconductor structure comprising:

• a common substrate;
• a first forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate and that has an nFET (n-doped Field Effect Transistor) and a pFET (p-doped Field Effect Transistor) and has a first β (effective width ratio) between the nFET and the pFET;
• and
• a second forksheet device that is adjacent to the first forksheet device on the common substrate and that has a second β between a second nFET and a second pFET, wherein the second β is different than the first β by at least 5 percent.