Transistor Source/Drain Regions and Methods of Forming the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kai-Lin Chuang, Kuo-Cheng Chiang, Chih-Hao Wang
Life of this patent
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Abstract
In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.
Claims20
A device comprising:
- first nanostructures;
- a first source/drain region adjacent the first nanostructures, a top surface of the first source/drain region extending above a top surface of the first nano structures, the first source/drain region contacting a first quantity of the first nanostructures;
- second nanostructures, the second nanostructures having the same dimensions as the first nanostructures;
- and
- a second source/drain region adjacent the second nanostructures, a top surface of the second source/drain region extending above a top surface of the second nano structures, the second source/drain region contacting a second quantity of the second nanostructures, the second quantity of the second nanostructures being greater than the first quantity of the first nanostructures.
A device comprising:
- first nanostructures;
- a first undoped semiconductor layer contacting a first dummy region of the first nanostructures;
- a first spacer on the first undoped semiconductor layer;
- a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nano structures;
- and
- a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.
A method comprising:
- patterning a first source/drain recess and a second source/drain recess in first nanostructures and second nanostructures, respectively, the first nanostructures having the same dimensions as the second nanostructures;
- growing a first semiconductor layer and a second semiconductor layer in the first source/drain recess and the second source/drain recess, respectively;
- increasing a first height of the first semiconductor layer as compared to a second height of the second semiconductor layer;
- and
- growing a first source/drain region and a second source/drain region over the first semiconductor layer and the second semiconductor layer, respectively.
Dependencies are inferred from the claim text.