Integrated circuit device

An integrated circuit device comprising:

• a fin-type active region extending along a first lateral direction on a substrate;
• a plurality of nanosheets facing a fin top surface of the fin-type active region at a position apart from the fin top surface of the fin-type active region, the plurality of nanosheets being at vertical distances from the fin top surface of the fin-type active region;
• a gate line surrounding each of the plurality of nanosheets on the fin-type active region, the gate line extending along a second lateral direction, wherein the second lateral direction intersects with the first lateral direction;
• an outer insulating spacer covering a sidewall of the gate line;
• and
• a source/drain region facing the plurality of nanosheets in the first lateral direction,
• wherein the source/drain region comprises:
• a buffer layer comprising portions respectively in contact with the plurality of nanosheets and a portion in contact with the fin-type active region, the buffer layer comprising a plurality of edge buffer portions having a smaller thickness than other portions thereof at a position adjacent to the outer insulating spacer;
• a plurality of local buffer patterns filling a plurality of spaces defined by the plurality of edge buffer portions and the outer insulating spacer, the plurality of local buffer patterns being separate from each other;
• and
• a main body layer in contact with each of the buffer layer and the plurality of local buffer patterns.

An integrated circuit device comprising:

• a fin-type active region extending along a first lateral direction on a substrate;
• a pair of nanosheet stacks facing a fin top surface of the fin-type active region in a vertical direction at a position apart from the fin top surface of the fin-type active region, each nanosheet stack comprising a plurality of nanosheets being at different vertical distances from the fin top surface of the fin-type active region;
• a pair of gate lines on the pair of nanosheet stacks on the fin-type active region, the pair of gate lines extending along a second lateral direction, wherein the second lateral direction intersects with the first lateral direction;
• a pair of outer insulating spacers respectively covering sidewalls of the pair of gate lines;
• and
• a source/drain region on the fin-type active region between the pair of nanosheet stacks, the source/drain region comprising a Si1-xGex layer (here, x≠0) doped with boron (B),
• wherein the source/drain region comprises:
• a buffer layer in contact with a plurality of nanosheets in each of the pair of nanosheet stacks, the buffer layer comprising an edge buffer portion having a smaller thickness than other portions thereof at a position adjacent to the plurality of outer insulating spacers, the edge buffer portion defining at least one wedge-type space along with an outer insulating spacer adjacent thereto from among the plurality of outer insulating spacers;
• at least one local buffer pattern filling the at least one wedge-type space;
• and
• a main body layer in contact with each of the buffer layer and the at least one local buffer pattern.