High-voltage semiconductor devices and methods of formation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWan-Jyun SYUE, Hsueh-Liang CHOU, Yi-Jen LO
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWan-Jyun SYUE, Hsueh-Liang CHOU, Yi-Jen LO
Estimating the term…
A high-voltage transistor may include a planar active region for a first source/drain active region, a second source/drain active region, and/or a channel active region. The planar active region(s) are included instead of a plurality of fin active regions to reduce the amount of surface area of the active regions in the high-voltage transistor that is in contact with surrounding dielectric layers of the high-voltage transistor. In other words, the planar active region(s) reduce the interface surface area between the silicon-based active regions of the high-voltage transistor and the surrounding oxide-based dielectric layers. The reduced interface surface area may reduce the occurrence of charge trapping in the high-voltage transistor, which may result in increased performance stability for the high-voltage transistor and/or may provide increased operational lifetime of the high-voltage transistor.
A semiconductor device, comprising:
A semiconductor device, comprising:
A method, comprising:
Dependencies are inferred from the claim text.