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US 2023/0420503 A1Published application
Common self aligned gate contact for stacked transistor structures
AssigneeInternational Business Machines Corporation
InventorsSu Chen Fan, Stuart Sieg, Xuan Liu, Junli Wang
Life of this patent
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Abstract
A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.
Claims20
A stacked semiconductor structure comprising:
- a top transistor stacked above a bottom transistor;
- a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.
A stacked semiconductor structure comprising:
- a top transistor stacked above a bottom transistor;
- a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor, wherein the single gate contact is self-aligned to the top gate conductor.
A stacked semiconductor structure comprising:
- a top transistor stacked above a bottom transistor;
- a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor, wherein the top gate conductor and the single gate contact comprise the same conductive material.
Dependencies are inferred from the claim text.