Single gated 3d nanowire inverter for high density thick gate soc applications

A semiconductor device, comprising:

• a substrate;
• a first transistor of a first conductivity type over the substrate, the first transistor comprising:
• a first semiconductor channel;
• a first gate electrode around the first semiconductor channel;
• a first gate dielectric between the first gate electrode and the first semiconductor channel, the first gate dielectric having a first composition;
• and
• a second transistor of a second conductivity type above the first transistor, the second transistor comprising:
• a second semiconductor channel;
• a second gate electrode around the second semiconductor channel;
• and
• a second gate dielectric between the second gate electrode and the second semiconductor channel, wherein the second gate dielectric has a second composition different than the first composition.

An electronic device comprising:

• a board;
• an electronic package electrically coupled to the board;
• and
• a die electrically coupled to the electronic package, wherein the die comprises:
• a substrate;
• a plurality of first semiconductor channels and a plurality of second semiconductor channels arranged in a vertical stack above the substrate;
• a first gate electrode surrounding the first semiconductor channels;
• a first gate dielectric between the first gate electrode and the first semiconductor channels, the first gate dielectric having a first composition;
• a second gate electrode surrounding the second semiconductor channels;
• and
• a second gate dielectric between the second gate electrode and the second semiconductor channels, wherein the second gate dielectric has a second composition different than the first composition.