Standalone high voltage galvanic isolation capacitors

A multi-chip module (MCM) comprising:

• a first die having a first integrated circuit configured to operate at a first voltage level;
• a second die having a second integrated circuit configured to operate at a second voltage level, a difference between the first voltage level and the second voltage level being greater than about 500 V;
• and
• a third die containing a first capacitor coupled in series with a second capacitor through a bottom metal plate, the first capacitor including a first upper metal plate having a first area, the first upper metal plate being coupled to the first integrated circuit, the second capacitor including a second upper metal plate having a second area, the second upper metal plate being coupled to the second integrated circuit, a ratio of the first area to the second area being 5.0 or greater.

A process of forming an integrated circuit chip comprising:

• forming a pre-metal dielectric (PMD) layer on a semiconductor substrate, the PMD layer having a first thickness;
• forming a lower metal plate over the PMD layer;
• forming an inter-level dielectric (ILD) layer on the lower metal plate, the ILD layer having a second thickness, a ratio of the first thickness to the second thickness being between about 1.0 and about 1.55;
• and
• forming a first upper metal plate and a second upper metal plate over the ILD layer, the first upper metal plate having a first area, the second upper metal plate having a second area, and a ratio of the first area to the second area being greater than 5.0.