Integrated circuit devices including metallic source/drain regions

An integrated circuit device comprising:

• a substrate;
• an upper transistor on the substrate, wherein the upper transistor comprises upper source/drain regions and an upper channel region between the upper source/drain regions;
• a lower transistor between the substrate and the upper transistor, wherein the lower transistor comprises lower source/drain regions and a lower channel region between the lower source/drain regions, and one of the lower source/drain regions comprises a first metal layer;
• and
• a lower contact that is in the substrate and comprises a second metal layer contacting the first metal layer of the one of the lower source/drain regions.

A method of forming an integrated circuit device, the method comprising:

• forming a preliminary transistor stack on a substrate, the preliminary transistor stack comprising an upper channel region and a lower channel region that is between the substrate and the upper channel region;
• forming first and second lower source/drain regions that respectively contact opposing side surfaces of the lower channel region and comprise a first semiconductor material;
• forming first and second upper source/drain regions that respectively contact opposing side surfaces of the upper channel region and comprise a second semiconductor material;
• and
• replacing at least one of the first semiconductor material of the first lower source/drain region and the second semiconductor material of the first upper source/drain region with a metal layer.