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US 2023/0420437 A1Published application
Three dimensional (3d) chiplet and methods for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChieh-Yen Chen, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu
Life of this patent
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Abstract
A semiconductor structure, includes a logic die, a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond, and a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.
Claims20
A semiconductor structure, comprising:
- a logic die;
- a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond;
- and
- a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.
1 more element
A method of forming a semiconductor structure, the method comprising:
- forming a first direct bond between a first memory die and a second memory die;
- connecting a first oxide layer of a logic die with a second oxide layer of the second memory die;
- forming a first through silicon via (TSV) in the logic die so as to extend across the first and second oxide layers and electrically connect the logic die to the first memory die and second memory die;
- and
- forming a metal layer on the first TSV to connect the first TSV to a logic circuit in the logic die.
2 more elements
A semiconductor structure, comprising:
- a base die chiplet;
- and
- a top die chiplet bonded to the base die chiplet, the top die chiplet comprising:
- a logic die;
- a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond;
- and
- a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.
4 more elements
Dependencies are inferred from the claim text.