US 2023/0420436 A1Published application

Package architecture with vertical stacking of integrated circuit dies having planarized edges and multi-side routing

AssigneeIntel Corporation

InventorsSagar Suthram, Ravindranath Vithal Mahajan, Debendra Mallik, Omkar G. Karhade, Wilfred Gomes, Pushkar Sharad Ranade, Abhishek A. Sharma, Tahir Ghani, Anand S. Murthy, Nitin A. Deshpande

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Abstract

Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.

Claims20

Dependent claims

An integrated circuit (IC) die, comprising:

a first region having a first surface and a second surface, the first surface being orthogonal to the second surface;
a second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface;
and
a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a fourth surface, the fourth surface being coplanar with the first surface and the third surface;
wherein:
the first region and the third region comprise:
a dielectric material;
a plurality of layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface;
conductive vias through the dielectric material, the conductive vias being orthogonal to the conductive traces;
and
bond-pads on the first surface and the fourth surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface and the fourth surface, and
the second region comprises a material different from the dielectric material.

9 more elements

A microelectronic assembly, comprising:

a first IC die coupled to a second IC die by interconnects on a first surface of the first IC die and a second surface of the second IC die such that the first surface is in contact with the second surface,
wherein:
the interconnects comprise dielectric-dielectric bonds and metal-metal bonds,
the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC die,
the first IC die comprises a substrate between metallization stacks,
the metallization stacks are attached to the substrate on opposing planar interfaces,
the planar interfaces are orthogonal to the first surface,
the metallization stacks comprise respective pluralities of layers of conductive traces in a dielectric material, and
the first bond-pads comprise portions of the conductive traces exposed on the first surface.

6 more elements

A method of fabricating an IC die with planarized edges, comprising:

providing a wafer comprising IC dies, each IC die having a substrate with TSVs in the substrate;
coupling a first metallization stack to the substrate along a first planar interface;
and
coupling a second metallization stack to the substrate along a second planar interface parallel to the first planar interface on an opposing side of the substrate.

1 more element

Dependencies are inferred from the claim text.