Package architecture of photonic system with vertically stacked dies having planarized edges

A microelectronic assembly, comprising:

• a first IC die coupled to a second IC die by interconnects on a first surface of the first IC die and a second surface of the second IC die such that the first surface is in contact with the second surface,
• wherein:
• the interconnects comprise dielectric-dielectric bonds and metal-metal bonds,
• the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC die,
• the first IC die comprises a substrate between a first interconnect stack and a second interconnect stack attached to the substrate on opposing planar interfaces,
• the first interconnect stack comprises a plurality of layers of conductive traces in a dielectric material,
• the first bond-pads comprise portions of the conductive traces exposed on the first surface,
• the planar interfaces are orthogonal to the first surface, and
• the second interconnect stack comprises optical structures of a photonic IC.

A method of fabricating an integrated photonic IC, comprising:

• providing a first wafer comprising a first substrate and a first interconnect stack directly coupled to the first substrate along a first planar interface, wherein the first substrate comprises a first active circuitry proximate to the first planar interface;
• providing a second wafer comprising a second substrate and a second interconnect stack directly coupled to the second substrate along a second planar interface, wherein the second substrate comprises a second active circuitry proximate to the second planar interface and the second planar interface is parallel to the first planar interface;
• bonding the first interconnect stack of the first wafer and the second interconnect stack of the second wafer along a third planar interface, wherein the third planar interface is parallel to the first and second planar interfaces;
• attaching a carrier to an exposed surface of the second wafer;
• turning over to expose a surface of the first wafer, the exposed surface of the first wafer being parallel to the first, second and third planar interfaces;
• forming a third interconnect stack over the exposed surface of the first wafer;
• singulating into individual IC dies;
• and
• planarizing surfaces of the individual IC dies such that portions of conductive traces in the third interconnect stack are exposed on surfaces of the individual IC dies orthogonal to the first, second, and third planar interfaces.