Package architecture with vertical stacking of integrated circuit dies having planarized edges

A microelectronic assembly, comprising:

• a first IC die coupled to a second IC die by interconnects on a first surface of the first IC die and a second surface of the second IC die such that the first surface is in contact with the second surface,
• wherein:
• the interconnects comprise dielectric-dielectric bonds and metal-metal bonds,
• the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC die,
• the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface,
• the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and
• the first bond-pads comprise portions of the conductive traces exposed on the first surface.

A method of fabricating an IC die with planarized edges, comprising:

• providing a first carrier with a wafer bonded thereto, the wafer comprising a plurality of IC dies fabricated thereon, each IC die comprising a substrate attached to a metallization stack along a planar interface, the metallization stack comprising conductive traces parallel to the planar interface, each IC die being as wide and as long as any other IC die in the wafer;
• positioning the first carrier with the wafer horizontally such that the first carrier is beneath the wafer and a surface of the wafer opposite to the first carrier is facing upwards;
• forming an interface layer on the surface of the wafer opposite to the first carrier, the interface layer comprising a material including silicon and oxygen;
• attaching another wafer to the interface layer;
• repeating forming the interface layer and attaching another wafer until a desired height is obtained over the first carrier;
• attaching a second carrier on a surface of the topmost wafer opposite to the first carrier;
• singulating vertically into a plurality of stacks along surfaces of the IC dies configured to have bond-pads, the surfaces configured to have bond-pads being orthogonal to interfaces between adjacent wafers in the stack, such that each stack is as wide or as long as any one IC die;
• rotating each stack by ninety degrees such that the first carrier and the second carrier are oriented vertically and the interfaces between adjacent wafers are vertical;
• attaching the plurality of the stacks to a horizontal bonding surface of a third carrier such that the interfaces between adjacent wafers are orthogonal to the bonding surface of the third carrier;
• depositing a dielectric material around the plurality of stacks over the bonding surface of the third carrier such that a continuous horizontal surface is exposed opposite to the third carrier;
• planarizing the continuous horizontal surface to expose bond-pads of the IC dies in the wafer, each bond-pad comprising a portion of respective conductive traces;
• removing the dielectric material;
• and
• separating IC dies from each stack.