Semiconductor chip and semiconductor package including the same

A semiconductor chip, comprising:

• a semiconductor substrate that includes a first surface and a second surface opposite to each other;
• a pad insulating layer disposed on the second surface of the semiconductor substrate;
• a through electrode structure that partially penetrates the semiconductor substrate but does not penetrate the pad insulating layer, wherein the through electrode structure includes a conductive plug and a plug barrier layer that surrounds the conductive plug;
• an insulating liner that at least partially surrounds the through electrode structure;
• an insulating sidewall that penetrates the semiconductor substrate, the pad insulating layer and the insulating liner, and includes a pad hole formed therein;
• and
• a bonding pad structure disposed in the pad hole and that partially and vertically overlaps the pad insulating layer and partially penetrates the through electrode structure,
• wherein the through electrode structure includes a first through electrode structure and a second through electrode structure, and
• an upper surface of the first through electrode structure is vertically closer to the second surface of the semiconductor substrate than an upper surface of the second through electrode structure.

A semiconductor package, comprising:

• a first semiconductor chip;
• and
• a second semiconductor chip disposed on the first semiconductor chip,
• wherein the second semiconductor chip includes an upper pad disposed on a lower surface thereof and an upper connection terminal that contacts the upper pad,
• wherein the first semiconductor chip comprises:
• a wiring structure;
• an interlayer insulating layer that surrounds the wiring structure;
• a semiconductor substrate disposed on the interlayer insulating layer;
• a pad insulating layer disposed on the semiconductor substrate;
• a through electrode structure that partially penetrates the semiconductor substrate but does not penetrate the pad insulating layer;
• an insulating liner that at least partially surrounds the through electrode structure;
• an insulating sidewall that penetrates the pad insulating layer, a part of the semiconductor substrate and at least a part of the insulating liner, and includes a pad hole formed therein;
• and
• a bonding pad structure that includes a pillar portion that fills the pad hole and a pad portion that covers a part of the pad insulating layer and contacts the through electrode structure, wherein
• the first semiconductor chip is electrically connected to the second semiconductor chip through a contact between the bonding pad structure and the upper connection terminal.