Semiconductor device with multiple dies

A semiconductor device comprising:

• a first die comprising ports;
• a second die comprising ports;
• and
• a multi-layer package substrate comprising:
• a first layer patterned to include pads for the ports of the first die and the second die;
• a second layer patterned to provide vias between the pads for the ports of the first die and pads for the ports of the second die and a third layer of the multi-layer package substrate;
• the third layer being patterned to provide traces that couple the vias coupled to ports of the first die to vias coupled to ports of the second die to couple the first die to the second die, the traces of the third layer of the multi-layer package substrate having a width;
• a fourth layer underlying the third layer;
• and
• a ground plane underlying the fourth layer, wherein a distance between traces of the third layer and the ground plane defines a height of the traces, and the width and the height of the traces are selected to provide a predetermined characteristic impedance across the traces.