Semiconductor device with power via

A method of manufacturing a semiconductor device, the method comprising:

• forming a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions;
• forming a gate cut region at cell boundaries between the first and second S/D epitaxial regions;
• forming a dielectric liner and a dielectric core in the gate cut region;
• forming a backside power rail (BPR) and a backside power distribution network (BSPDN);
• forming a power via passing through the dielectric core and connecting to the BPR and BSPDN;
• forming first metal contacts in contact with the first and second S/D epitaxial regions;
• and
• forming a via to backside power rail (VBPR) contact,
• wherein the dielectric liner separates the power via from the first S/D epitaxial region.

A semiconductor device comprising:

• a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions;
• a gate cut region at cell boundaries between the first and second S/D epitaxial regions;
• a first dielectric fill layer and a second dielectric fill layer formed in the gate cut region;
• and
• a backside power rail (BPR) connected to a backside power distribution network (BSPDN),
• wherein a portion of the second dielectric fill layer is removed and replaced with a power bar, which connects at least one of the first and second S/D epitaxial regions to the backside power rail.